The present invention relates to a memory controller, or in particular to a memory controller suitable for accessing a dynamic random access memory (DRAM) for storing image data or the like.
In recent years, with rapid extension of ownership of personal computers or the like, an increased number of DRAMs have been supplied as a main memory of the personal computers. At the same time, the price of the DRAM has decreased to such an extent that it has come to be employed also for an electronic equipment other than personal computers. The DRAM includes a synchronous DRAM (hereinafter referred to as SDRAM) which can be continuously written into and read from at higher speed in synchronism with the clock of an interface (hereinafter referred to as the burst transfer), a double data rate SDRAM (hereinafter referred to as DDR-SDRAM) having a burst transfer increased to a double speed by executing the burst transfer of the SDRAM in synchronism with both the leading edge and the trailing edge of the clock signal, and a Rambus DRAM (hereinafter referred to as RDRAM). Of these DRAMs, SDRAM can constitute an inexpensive, large-capacity memory, and therefore has come to be employed by more and more equipment. The SDRAM also has come to be used in place of the conventional expensive dedicated memory (VRAM) as a frame memory for temporarily holding the image data displayed on a display unit. The SDRAM are regulated by JEDEC Standard 21-C.
Examples of devices for accessing image data of the SDRAM include a display processing device for reading and transferring image data to a display unit and a graphic processing device for generating graphics data and writing them as image data to draw arbitrary graphics. The image data generated by a video input device can also be written and stored in the SDRAM. Further, a SDRAM can be configured as a unified memory in which a main memory and a frame memory for storing image data are integrated into a single memory. With an SDRAM configured as a unified memory, not only image data but also instruction codes and various data are accessed by processors, and therefore an efficient memory access is required.
In storing image data in a frame memory, the image data is assigned to a two-dimensional address space which is finite in horizontal and vertical directions in order to hold the image data in a data storage area. The image data are held as an arrangement in horizontal and vertical directions corresponding to a display screen (display pixels) of a display device. The image data of each pixel corresponding to the display screen is configured of several to several tens of bits, and the bit length of the image data of one pixel is determined by the data format.
In storing image data in the SDRAM as a frame memory, on the other hand, the data storage area is divided into a plurality of, say four, banks, each of which is in turn divided into several pages, and each page is assigned a row address. In setting an address in the frame memory having this configuration, the linear address mapping and the tile address mapping are employed.
The linear address mapping is a method in which assuming that a horizontal arrangement of pixel data is a line, the pixel data arranged in horizontal direction (image data corresponding to the pixels of the display screen arranged in horizontal direction) are assigned horizontally continuous addresses and all the display pixels in a line are assigned the same row address, i.e. the row address of the same page. In this case, the pixel data of a different line is assigned a different row address of the same bank, or the row address of a different bank. In other words, the pixel data of a different line are assigned a different page.
The tile address mapping, on the other hand, is a method in which the pixel data in a rectangle (hereinafter referred to as the tile) having 32 bytes in horizontal direction and 16 lines in vertical direction are assigned continuous addresses, and all the pixel data in each tile are assigned the same row address, i.e. the same page. In this case, the pixel data (image data) of a different tile are assigned a different row address of the same bank, or the row address of a different bank. In other words, the pixel data of a different tile are assigned a different page.
The SDRAM requires the refresh operation for holding data, and in accessing the SDRAM, the page to be accessed is designated by a row address, and all the data belonging to the designated page are activated by being transferred to and amplified by a sense amplifier. Of the data thus activated, only the data designated by a column address are accessed by the read or write operation. In this case, the data of the same page can be continuously accessed. For different pages, however, all the data in the sense amplifier are required to be precharged by being returned to the original page, after which all the data belonging to the page to be accessed are activated by being transferred to and amplified by a sense amplifier.
In this way, the data belonging to the same page can be continuously accessed, and therefore the access efficiency can be improved. When accessing a different page, however, a page mishit occurs. In this case, the page to be accessed is precharged and activated before being accessed, resulting in a lower memory access efficiency. In accessing the SDRAM, therefore, a page mishit is desirably reduced, and in setting the address mapping in the SDRAM, the requirements of the device functions must be met.
Specifically, assume an application of the linear address mapping to the SDRAM used for a display processing device. In view of the fact that the display processing device makes access in one direction either from left to right or from right to left on a line, a page mishit is not caused and can be suppressed as long as the same line is being accessed. In an application of the tile address mapping to the SDRAM used for the display processing device, however, a page mishit is often caused. This is by reason of the fact that the display processing device can start access with an arbitrary address, and the scroll of the image displayed and the boundaries of a plurality of display image planes (hereinafter referred to as the planes) are set at arbitrary positions. An access from the display processing device to the pixel data continuous along a line of the SDRAM using the tile address mapping, therefore, goes over the tile boundary (the boundary between tiles). Thus, a page mishit occurs each time a tile boundary is crossed, resulting in a reduced memory access efficiency.
In the case where a graphic processing device accesses the SDRAM using the linear address mapping, in contrast, the continuous access is possible and the page mishit can be reduced for horizontal drawing. In the case of vertical or diagonal plotting, however, a different page is accessed for each cycle, and therefore a page mishit occurs for each drawing cycle, thereby reducing the memory access efficiency.
Specifically, the graphic processing device is adapted to generate arbitrary graphics in accordance with a draw instruction code given and write the image data on the generated graphics in a two-dimensional address space of the SDRAM. Also, the graphics drawn are configured of straight lines and curves of arbitrary angles. Therefore, the addresses to be accessed are continuous in horizontal direction, in vertical direction or in diagonal direction. As a result, as long as the tile address mapping is set in the SDRAM used for the graphic processing device, a page mishit occurs only when crossing a tile boundary regardless of the direction of access, horizontal, vertical or diagonal. It is therefore possible to reduce the page mishit more than when using the linear address mapping. For this reason, the tile address mapping is more preferable for the graphic processing, and many equipment with a frame memory realized by the SDRAM employ the tile address mapping.
A sort of real time operation is required for reading image data by the display processing device. Specifically, unless the read operation of the image data is completed within a predetermined time, the image displayed on the display unit comes to flicker. For preventing the image flicker, the arbitration of accesses to the SDRAM is important as well as improving image data access efficiency by suppressing the page mishit of the SDRAM. Especially, the unified memory configuration often causes the contention between the access from the graphic processing device and the accesses from other devices such as processors. Therefore, how to suppress the delay of image data access due to the access contention is crucial.
A method for accessing a SDRAM efficiently as a frame memory is proposed in JP-A-8-255107. In this method, the address to be accessed is compared with the address of the preceding access to decide on a page hit. In the case where a page mishit occurs, the bank is precharged and a new page is activated. Then, the write or read operation is executed. In the case of a page hit, on the other hand, the write or read operation is executed immediately without bank precharge or page activation. Further, an address counter is included which is incremented successively by a predetermined unit count. Thus, it is possible for the display processing device to read the image data efficiently by suspending access to a given page immediately before access to a different page when the different page is to be accessed while the given page is being continuously accessed.
In JP-A-8-255107, however, the address to be accessed and the address of the preceding access are simply compared with each other for page hit decision of the SDRAM. Therefore, the interleave access to a plurality of banks (a method of distributing the accesses to a plurality of banks to improve the access efficiency by individual activation of the pages of each of two or four banks) which is the feature of the SDRAM cannot be utilized for improving the access efficiency.
Also, according to JP-A-8-255107, for reading the image data by the display processing device, in the case where a different page is accessed while the data of a given page are being continuously accessed, a page mishit is prevented by suspending the ongoing access. When executing the succeeding access, however, a page mishit occurs after all, and therefore the precharge and the activation of the banks are not avoidable.
Further, JP-A-8-255107 fails to take into consideration the arbitration to meet the requirement for the real time operation by the display processing device in the case where a plurality of accesses compete with each other.
The object of the present invention is to provide a memory controller making possible efficient access to a dynamic random access memory.
In order to achieve the object described above, according to the present invention, there is provided a memory controller comprising means for receiving a request for accessing a dynamic random access memory having a data storage area divided into a plurality of banks each divided into a plurality of pages, and memory control means for activating the page to be accessed, based on the access request and, before executing the access to the activated page, executing the advance precharge of the page to be accessed subsequently.
In the memory controller according to this invention, after activation of the page to be accessed and before accessing the activated page, the bank or the page to be accessed next or subsequently is precharged in advance. When accessing the bank or the page to be accessed next or subsequently, therefore, the particular bank or the page, as the case may be, is not required to be precharged and can be accessed by the read or write operation after activation without precharge. Even in the case where a different page is accessed due to a page mishit, therefore, the time is saved after precharge to activation. Thus, the time overhead can be shortened and an efficient access can be achieved. As a result, the data amount accessible per unit time can be increased thereby contributing to an improved band width.
On the other hand, assume that while an access request from a given processor unit is selected and under execution, an access request of higher priority, e.g. an access request of higher requirement for real time operation is newly input and access requests from a plurality of processor units (devices) contend each other. The access based on the selected access request is suspended, and the newly input access request is given priority of access. Even in the case where a plurality of access requests contend each other, therefore, an access request of higher priority (access request of higher requirement for real time operation) can be executed in priority, thereby suppressing the access delay for image data which otherwise might be caused by the contention between access requests.
In the case where the advance precharge is not conducted, on the other hand, the status of the dynamic random access memory is managed in such a manner that an access is executed in accordance with the status of the memory. Therefore, the memory can be accessed positively in accordance with the memory status. Further, in the case where the advance precharge is not conducted and a page mishit is caused, the precharge and activation are carried out within the shortest timing in keeping with the minimum cycles between activation and precharge and the minimum cycles between precharge and activation by reference to the information on the active flag, the row address buffer RAS counter and the RP counter.